1. Field of the Invention
The present invention generally relates to double gate metal-oxide-semiconductor field effect transistors (MOSFETs) and, more particularly, to an improved method for forming and isolating a double gate backgate MOSFET device.
2. Description of the Related Art
Double gate metal-oxide-semiconductor field effect transistor (MOSFET) designs have been studied as one way to extend traditional single-gate MOSFET scaling into the next few generations of miniaturization. Where traditional single gate MOSFETs need precipitously thinned gate oxides and precisely controlled dopant distributions at levels approaching solid solubility in order to control device short channel effects and produce good on-to-off current ratios (Y. Taur and S. Novak, 1997 IEDM Tech. Digest, IEEE, Piscataway, N.J., USA, p. 215; incorporated herein by reference), devices with a backgate are expected to deliver improved device characteristics, improved short channel effects and increased drive current, at the same and higher gate oxide thickness, with silicon channels with reduced doping (H. S. Wong, D. J. Frank, and P. M. Solomon, 1998 IEDM Tech. Digest, IEEE, Piscataway, N.J., USA, p. 407; incorporated herein by reference). Recent simulations show that with a backgate, device characteristics are most dependent on channel thickness (Wong et al., supra). Other parameters of importance to the device behavior are the alignment of the top and bottom gates and the overlap of the two gates and the source/drain area.
A number of double gate devices have been proposed and fabricated, but a truly manufacturable process has not been identified. A double gate device fabricated on standard silicon wafers by growing epitaxial silicon through placeholder gates which are replaced later with polysilicon has produced the best top to bottom gate alignment.
However, the epitaxially grown channel is very difficult and slow to grow, and does not have top electric quality (H. S. Wong, K. K. Chan, Y. Taur, 1998 IEDM Tech. Digest, IEEE, Piscataway, N.J., USA, p. 427; incorporated herein by reference). Defining and planarizing backgate structures and then bonding the backgate structures to a silicon wafer has been attempted. However, aligning the top gates to bottom gates hidden under a silicon channel has not yet produced devices with adequate overlay (I. A. Yang, A. Lochtefeld, and D. A. Antoniadis, Proc. 1996 IEEE Int. SOI Conf, IEEE, Piscataway, N.J., USA, p. 106; incorporated herein by reference).
A previous patent by Solomon and Wong, 5,773,331, solves many of these problems. As illustrated in FIG. 1, the prior art of Solomon and Wong uses a starting silicon wafer 10 having blanket layers of buried oxide 12, backgate material 14, backgate dielectric 16 and crystalline silicon channel 18. The backgate material 14 may be polysilicon or metal. The wafers can be made by bonding and etch back techniques, by using either high dose implantation and subsequent layer splitting, or by double SIMOX.
The Solomon and Wong device is made by patterning the top half of the device in a way similar to a conventional MOSFET, and then using the top half of the device as an etch mask for the self-aligned patterning of the backgate. This produces a smaller total device area than an epitaxial-Si based device which must include an extra open area for the Si seed. In addition, using the top half of the device as an etch mask allows better top-to- bottom gate overlay than pre-patterned backgate approaches and further allows the use of metallic backgate materials.
The process of Solomon and Wong has limitations. One limitation is the dependence on sidewall isolation. The Solomon and Wong device has very severe topography, which leads to debris from each reactive ion etching step to build up both outside the topgate and bottom gate mesa patterns as well as inside the source/drain well areas. Extensive simulations of this device have shown that extremely precise alignment of the different masks used to make the top and bottom gate mesas and the source/drain wells is necessary to avoid shorting of the top gate to the sidewall source/drain. It is also necessary to increase the overlap of the top and bottom gates in the plane of the gate contacts to reduce the likelihood of shorting.
Further, in the Solomon and Wong design, the source and drain are very likely to be connected without the addition of an additional mask. The alignment and resolution requirements of the first level of metal is also very critical in this design, since the metal has to separately contact the narrow and closely spaced sidewall source/drain silicide contacts.
An alternative proposed by Solomon and Wong is to use chemical mechanical polishing (CMP) to separate source from drain. However, such a proposed method is difficult to implement because of the lack of a common reference level for the CMP at this step.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional methods for producing MOSFET backgate devices, the present invention has been devised, and it is an object of the present invention to provide a method for using chemical mechanical polishing (CMP) for isolation and planarization of the MOSFET backgate device.
The invention, in one form thereof, is a method of forming a backgate for a double gate metal-oxide-semiconductor field effect transistor (MOSFET). The method comprising the steps of supplying a bottom gate mesa stack, planarizing the bottom mesa stack using chemical mechanical polishing (CMP) to isolate the bottom gate mesa, forming a topgate mesa stack, patterning and isolating the topgate, trimming the backgate using the topgate as a mask to transfer a pattern to the bottom gate, and isolating the trimmed backgate. In one particular embodiment, the topgate used as a mask to trim the backgate includes using the isolated topgate or the topgate plus source/drain areas. In another embodiment, CMP is used to planarize the topgate mesa and then the edges of the topgate mesa are etched to form the active gate and wells in which the source and drain are formed.
Objects of the present invention are to reduce or eliminate the risk of source-to-drain shorts, reduce or eliminate the risk of gate to source/drain shorts, decrease the top and bottom gate overlap capacitance, increase the tolerance of the device layout to lithography overlay errors, and reduce the number of critical lithography levels. Further, this inventive method includes improved manufacturability of backgate MOSFET devices over conventional methods.